Structured ASIC are generally fixed size monolithic chips with metal/via programmablity to control some amount of wiring (hardcopy, easic,..). Modern FPGAs with a mix of har coded blocks (serde, cpus, DSP) connected by NoCs and PL is another example. The front end transistor layers are fixed.
The Zero ASIC platform does "late binding" by wiring together different chiplets (cpu, lm, fpga, serdes,...) in the package. Both approaches are addressing the same problem of flexibility vs performance, but the approaches are very different.
The Zero ASIC platform does "late binding" by wiring together different chiplets (cpu, lm, fpga, serdes,...) in the package. Both approaches are addressing the same problem of flexibility vs performance, but the approaches are very different.